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| S29NS-P MirrorBitTM Flash Family S29NS512P S29NS256P S29NS128P 512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous Read/Write, Multiplexed MirrorBit Flash Memory Data Sheet (Advance Information) S29NS-P MirrorBitTM Flash Family Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S29NS-P_00 Revision A Amendment 1 Issue Date February 20, 2007 Data Sheet (Advance Information) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local sales office. 2 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 S29NS-P MirrorBitTM Flash Family S29NS512P S29NS256P S29NS128P 512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V Burst Simultaneous Read/Write, Multiplexed MirrorBit Flash Memory Data Sheet (Advance Information) Features Single 1.8 V read/program/erase (1.70-1.95 V) 90 nm MirrorBit Technology Multiplexed Data and Address for reduced I/O count Simultaneous Read/Write operation Full/Half drive output slew rate control 32-word Write Buffer Sixteen-bank architecture consisting of 64/32/16 MB for NS512/256/128P, respectively Four 32 KB sectors at the top of memory array (NS256/128P) 512 128KB sectors (NS512P), 255/127 128KB sectors (NS256/ 128P) Programmable linear (8/16/32) with or without wrap around and continuous burst read modes Secured Silicon Sector region consisting of 128 words each for factory and customer 20-year data retention (typical) Cycling Endurance: 100,000 cycles per sector (typical) RDY output indicates data available to system Command set compatible with JEDEC (42.4) standard Hardware (WP#) protection of highest two sectors Top Boot sector configuration (NS256/128P) Handshaking by monitoring RDY Offered Packages - NS512P: 64-ball FBGA (8 mm x 9.2 mm) - NS256P/NS128P: 44-ball FBGA (6.2 mm x 7.7 mm) Low VCC write inhibit Persistent and Password methods of Advanced Sector Protection Write operation status bits indicate program and erase operation completion Suspend and Resume commands for Program and Erase operations Unlock Bypass program command to reduce programming time Synchronous or Asynchronous program operation, independent of burst control register settings VPP input pin to reduce factory programming time Support for Common Flash Interface (CFI) Performance Characteristics Read Access Times Speed Option (MHz) Max. Synch. Latency, ns (tIACC) Max. Synch. Burst Access, ns (tBACC) Max. Asynch. Access Time, ns (tACC) Max OE# Access Time, ns (tOE) 108 80 7.0 80 7.0 Typical Program & Erase Times Single Word Programming Effective Write Buffer Programming (VCC) Per Word Effective Write Buffer Programming (VPP) Per Word Sector Erase (16 Kword Sector) Sector Erase (64 Kword Sector) 30 s 6 s 4 s 350 ms 600 ms Current Consumption (typical values) Continuous Burst Read @ 108 MHz Simultaneous Operation 108 MHz Program Standby Mode 42 mA 60 mA 30 mA 20 A General Description The Spansion S29NS512/256/128P are MirrorBit Flash products fabricated on 90 nm process technology. These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using multiplexed data and address pins. These products can operate up to 108 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for the demanding wireless applications of today that require higher density, better performance, and lowered power consumption. Publication Number S29NS-P_00 Revision A Amendment 1 Issue Date February 20, 2007 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. Data Sheet (Advance Information) Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2. 3. 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions & Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Programmable Output Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Secured Silicon Sector Entry and Exit Command Sequences. . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 33 35 50 50 50 50 50 51 52 52 53 55 56 56 58 59 60 60 60 60 60 61 61 61 62 64 64 64 65 66 66 66 67 67 77 5. 6. 7. 8. 9. 10. 11. 12. 4 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figures Figure 3.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 7.2 Figure 7.3 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9 Figure 10.10 Figure 10.11 Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down . . 10 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down . . 11 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down . . 11 VDD064--64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P. . . . . . . . . . . . . . . . . . 12 VDE044--44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P . . . . . . . . . . . . . . 13 Synchronous Read Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PPB Program/Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 VCC Power-Up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 CLK Characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around . . . . . . . . . . . . . . . . 68 8-Word Linear Single Data Read Synchronous Burst without Wrap Around . . . . . . . . . . . . . 69 Asynchronous Mode Read with Latched Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Asynchronous Mode Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data# Polling Timings (During Embedded Algorithm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Toggle Bit Timings (During Embedded Algorithm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 5 Data Sheet (Advance Information) Tables Table 2.1 Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7 Table 6.8 Table 6.9 Table 6.10 Table 6.11 Table 6.12 Table 6.13 Table 6.14 Table 6.15 Table 6.16 Table 6.17 Table 6.18 Table 6.19 Table 6.20 Table 6.21 Table 6.22 Table 6.23 Table 6.24 Table 6.25 Table 6.26 Table 6.27 Table 6.28 Table 6.29 Table 7.1 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 11.6 6 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 S29NS512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 S29NS256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 S29NS128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Address Latency for 9 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Address Latency for 8 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Address Latency for 7 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 6 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 5 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 4 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Address Latency for 3 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Address Latency for 2 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Burst Address Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Autoselect Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Single Word Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Programmable Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Secured Silicon SectorSecure Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) . . . . . . . . . . . . . .62 Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) . . . . . . . . . . . . . . . . . . .62 Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) . . . . . . . . . . . . . . . . .63 DC Characteristics--CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 VCC Power-Up with No Ramp Rate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 CLK Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Synchronous Wait State Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Asynchronous Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Example of Programmable Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 1. Ordering Information The ordering part number is formed by a valid combination of the following: S29NS 512 P xx BJ W 00 0 Packing Type 0 = Tray (standard; (Note 1)) 3 = 13-inch Tape and Reel Model Number 00 = Standard Temperature Range W = Wireless (-25C to +85C) Package Type & Material Set BJ = Very Thin Fine-Pitch BGA,Lead (Pb)-free LF35 Package Speed Option (Burst Frequency) 0P = 66 MHz 0S = 83 MHz AB = 108 MHz Process Technology P = 90 nm MirrorBitTM Technology Flash Density 512 =512 Mb 256 =256 Mb 128 =128 Mb Product Family S29NS = 1.8 Volt-only Simultaneous Read/Write, Burst Mode Multiplexed Flash Memory Valid Combinations Base Ordering Part Number S29NS512P S29NS256P S29NS128P Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S29 and packing type designator from ordering part number. 0P, 0S, AB BJW (Lead (Pb)-free, LF35) 0, 3 (1) 00 6.2 mm x 7.7 mm, 44-ball Speed Option Package Type Package Type, Material, & Temperature Range Packing Type Model Number 8.0 mm x 9.2 mm, 64-ball Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 7 Data Sheet (Advance Information) 2. Input/Output Descriptions & Logic Symbol Table 2.1 identifies the input and output package connections provided on the device. Table 2.1 Input/Output Descriptions Symbol A24 - A16 A23 - A16 A22 - A16 A/DQ15 - A/DQ0 CE# OE# WE# VCC VCCQ VSS VSSQ NC RDY CLK Type Input Input Input I/O Input Input Input Supply Supply I/O I/O No Connect Output Input Address inputs, S29NS512P Address inputs, S29NS256P Address inputs, S29NS128P Multiplexed Address/Data input/output Chip Enable. Asynchronous relative to CLK for the Burst mode. Output Enable. Asynchronous relative to CLK for the Burst mode Write Enable Device Power Supply Input/Output Power Supply (must be ramped simultaneously with VCC) Ground Input/Output Ground No Connected internally Ready. Indicates when valid burst data is ready to be read The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15 - A0 are multiplexed, address bits Amax - A16 are address only). VIL = for asynchronous mode, indicates valid address; for burst mode, cause staring address to be latched on rising edge of CLK. VIH = device ignores address inputs Hardware Reset. Low = device resets and returns to reading array data. Write Protect. At VIL, disables program and erase functions in the four top sectors. Should be at VIH for all other conditions. Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL,disables all program and erase functions. Should be at VIH for all other conditions. Reserved for future use Description AVD# Input RESET# WP# Input Input VPP Input RFU Reserved 8 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 3. Block Diagrams Figure 3.1 Simultaneous Operation Circuit VCC Bank Address Y-Decoder VSS VCCQ VSSQ Latches and Control Logic DQ15-DQ0 Bank 0 Amax-A0 X-Decoder OE# Bank Address Latches and Control Logic Y-Decoder DQ15-DQ0 Bank 1 WP# VPP RESET# WE# CE# AVD# RDY A/DQ15-A/DQ0 ?Amax-A0 X-Decoder DQ15-DQ0 Status STATE CONTROL & COMMAND REGISTER ?Amax-A16 Control X-Decoder Latches and Control Logic Y-Decoder Bank Address Bank (n-1) DQ15-DQ0 ?Amax-A16 X-Decoder Bank Address Latches and Control Logic Y-Decoder Bank (n) DQ15-DQ0 Notes 1. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P. 2. Bank (n) = 15 for NS512P/ NS256P/ NS128P. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 9 Data Sheet (Advance Information) 4. Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the OPN. 4.1 Related Documents The following documents contain information relating to the S29NS-P devices. Click on the title or go to www.spansion.com, or request a copy from your sales office. Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4.2 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. 64-Ball Fine-Pitch Grid Array, S29NS512P Figure 4.1 64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P Top View, Balls Facing Down 1 A nc B nc 2 3 4 5 6 7 8 9 10 11 12 13 14 C DNU D F-RDY E F-VCCQ F F-VSS G A/DQ15 A/DQ14 H DNU J DNU DNU F-VCCQ F-VSSQ DPD F-VCCQ DNU DNU DNU Do Not Use F-VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 F-VCCQ A/DQ1 A/DQ0 A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8 F-OE# Reserved for Future Use A16 A20 F-ADV# A23 F-RST# F-WP# A18 F-CE# F-VSSQ No Connect A21 F-VSS F-CLK F-VCC F-WE# F-ACC A19 A17 A22 Flash Only DNU F-VSS A24 F-VCC F-VSS F-VCC A25 DNU DNU Legend K nc nc Figure 2.1. 10 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Figure 4.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256P Top View, Balls Facing Down NC NC A1 RDY B1 VCCQ C1 VSS D1 A2 A21 B2 A16 C2 A/DQ7 D2 A3 VSS B3 A20 C3 A/DQ6 D3 VSSQ A4 CLK B4 AVD# C4 A/DQ13 D4 A/DQ5 A5 VCC B5 A23 C5 A/DQ12 D5 A/DQ4 A6 WE# B6 RESET# C6 A/DQ3 D6 A7 VPP B7 WP# C7 A/DQ2 D7 A8 A19 B8 A18 C8 A/DQ9 D8 VCCQ A9 A17 B9 CE# C9 A/DQ8 D9 A/DQ1 A10 A22 B10 VSSQ C10 OE# D10 A/DQ0 A/DQ15 A/DQ14 A/DQ11 A/DQ10 NC NC 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Figure 4.3 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128P Top View, Balls Facing Down NC NC A1 RDY B1 VCCQ C1 VSS D1 A2 A21 B2 A16 C2 A/DQ7 D2 A3 VSS B3 A20 C3 A/DQ6 D3 VSSQ A4 CLK B4 AVD# C4 A/DQ13 D4 A/DQ5 A5 VCC B5 NC C5 A/DQ12 D5 A/DQ4 A6 WE# B6 RESET# C6 A/DQ3 D6 A7 VPP B7 WP# C7 A/DQ2 D7 A8 A19 B8 A18 C8 A/DQ9 D8 VCCQ A9 A17 B9 CE# C9 A/DQ8 D9 A/DQ1 A10 A22 B10 VSSQ C10 OE# D10 A/DQ0 A/DQ15 A/DQ14 A/DQ11 A/DQ10 NC NC February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 11 Data Sheet (Advance Information) VDD064--64-Ball Very Thin Fine-Pitch Ball Grid Array Figure 4.4 VDD064--64-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS512P 10 D A D1 e A1 CORNER A1 CORNER INDEX MARK 10 9 8 7 6 5 4 3 2 NF2 1 NF1 e A B C D E 7 E 0.50 NF4 NF3 SE E1 F TOP VIEW A A1 A2 B 1.00 SD 7 Ob 0.10 C 6 O 0.05 M C O 0.15 M C A B SEATING PLANE C 0.08 C BOTTOM VIEW SIDE VIEW NOTES: PACKAGE JEDEC VDD 064 N/A 8.00 mm x 9.20 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N Ob 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT 0.35 BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 4. e REPRESENTS THE SOLDER BALL GRID PITCH. MIN 0.86 0.20 0.66 7.90 9.10 NOM ----0.71 8.00 9.20 4.50 2.50 10 6 64 MAX 1.00 --0.76 8.10 9.30 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3533 \ 16-038.27 \ 12.13.05 0.25 0.30 0.50 0.25 e SD / SE 12 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) VDE44-44-Ball Very Thin Fine-Pitch Ball Grid Array, 6.2mm x 7.7 mm Figure 4.5 VDE044--44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS128/256P A1 CORNER INDEX MARK 10 D A D1 A1 CORNER 10 9 8 7 6 5 4 3 2 1 NF2 NF1 e A E 1.00 NF4 NF3 B C D SE 7 E1 1.00 TOP VIEW B SD b 7 6 0.05 M C 0.15 M C A B A A1 A2 0.10 C BOTTOM VIEW SIDE VIEW SEATING PLANE C 0.08 C NOTES: PACKAGE JEDEC VDE 044 N/A 7.70 mm x 6.20 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE ? 0.25 MIN 0.86 0.20 0.66 7.6 6.1 NOM ----0.71 7.7 6.2 4.50 1.50 10 4 44 0.30 0.50 BSC. 0.25 BSC. 0.35 MAX 1.00 --0.76 7.8 6.3 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ? THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3308.2 \ 16-038.9L February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 13 Data Sheet (Advance Information) 5. Product Overview The S29NS-P family consists of 512, 256, and 128 Mb, 1.8 volts-only, simultaneous read/write burst mode, multiplexed Flash device optimized for today's wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 32, 16, or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-word, 16-word, or 32-word aligned group) with or without wrap around. These flash devices multiplex the data and addresses for reduced I/O count. These products also offer single word programming or a 32-word buffer for programming with program/erase and suspend functionality. Additional features include: Advanced Sector Protection methods for protecting sectors as required 256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time Programmable. 5.1 Memory Map The S29NS512/256/128P Mb devices consist of 16 banks organized as shown in Tables 5.1 - 5.3. Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 1 of 8) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 Bank 1 Bank 0 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 14 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 2 of 8) Bank Sector SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 Bank 2 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh Bank 3 Bank Sector SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 15 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 3 of 8) Bank Sector SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 Bank 4 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 800000h-80FFFFh 810000h-81FFFFh 820000h-82FFFFh 830000h-83FFFFh 840000h-84FFFFh 850000h-85FFFFh 860000h-86FFFFh 870000h-87FFFFh 880000h-88FFFFh 890000h-89FFFFh 8A0000h-8AFFFFh 8B0000h-8BFFFFh 8C0000h-8CFFFFh 8D0000h-8DFFFFh 8E0000h-8EFFFFh 8F0000h-8FFFFFh 900000h-90FFFFh 910000h-91FFFFh 920000h-92FFFFh 930000h-93FFFFh 940000h-94FFFFh 950000h-95FFFFh 960000h-96FFFFh 970000h-97FFFFh 980000h-98FFFFh 990000h-99FFFFh 9A0000h-9AFFFFh 9B0000h-9BFFFFh 9C0000h-9CFFFFh 9D0000h-9DFFFFh 9E0000h-9EFFFFh 9F0000h-9FFFFFh Bank 5 Bank Sector SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range A00000h-A0FFFFh A10000h-A1FFFFh A20000h-A2FFFFh A30000h-A3FFFFh A40000h-A4FFFFh A50000h-A5FFFFh A60000h-A6FFFFh A70000h-A7FFFFh A80000h-A8FFFFh A90000h-A9FFFFh AA0000h-AAFFFFh AB0000h-ABFFFFh AC0000h-ACFFFFh AD0000h-ADFFFFh AE0000h-AEFFFFh AF0000h-AFFFFFh B00000h-B0FFFFh B10000h-B1FFFFh B20000h-B2FFFFh B30000h-B3FFFFh B40000h-B4FFFFh B50000h-B5FFFFh B60000h-B6FFFFh B70000h-B7FFFFh B80000h-B8FFFFh B90000h-B9FFFFh BA0000h-BAFFFFh BB0000h-BBFFFFh BC0000h-BCFFFFh BD0000h-BDFFFFh BE0000h-BEFFFFh BF0000h-BFFFFFh 16 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 4 of 8) Bank Sector SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 Bank 6 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range C00000h-C0FFFFh C10000h-C1FFFFh C20000h-C2FFFFh C30000h-C3FFFFh C40000h-C4FFFFh C50000h-C5FFFFh C60000h-C6FFFFh C70000h-C7FFFFh C80000h-C8FFFFh C90000h-C9FFFFh CA0000h-CAFFFFh CB0000h-CBFFFFh CC0000h-CCFFFFh CD0000h-CDFFFFh CE0000h-CEFFFFh CF0000h-CFFFFFh D00000h-D0FFFFh D10000h-D1FFFFh D20000h-D2FFFFh D30000h-D3FFFFh D40000h-D4FFFFh D50000h-D5FFFFh D60000h-D6FFFFh D70000h-D7FFFFh D80000h-D8FFFFh D90000h-D9FFFFh DA0000h-DAFFFFh DB0000h-DBFFFFh DC0000h-DCFFFFh DD0000h-DDFFFFh DE0000h-DEFFFFh DF0000h-DFFFFFh Bank 7 Bank Sector SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range E00000h-E0FFFFh E10000h-E1FFFFh E20000h-E2FFFFh E30000h-E3FFFFh E40000h-E4FFFFh E50000h-E5FFFFh E60000h-E6FFFFh E70000h-E7FFFFh E80000h-E8FFFFh E90000h-E9FFFFh EA0000h-EAFFFFh EB0000h-EBFFFFh EC0000h-ECFFFFh ED0000h-EDFFFFh EE0000h-EEFFFFh EF0000h-EFFFFFh F00000h-F0FFFFh F10000h-F1FFFFh F20000h-F2FFFFh F30000h-F3FFFFh F40000h-F4FFFFh F50000h-F5FFFFh F60000h-F6FFFFh F70000h-F7FFFFh F80000h-F8FFFFh F90000h-F9FFFFh FA0000h-FAFFFFh FB0000h-FBFFFFh FC0000h-FCFFFFh FD0000h-FDFFFFh FE0000h-FEFFFFh FF0000h-FFFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 17 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 5 of 8) Bank Sector SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 SA270 Bank 8 SA271 SA272 SA273 SA274 SA275 SA276 SA277 SA278 SA279 SA280 SA281 SA282 SA283 SA284 SA285 SA286 SA287 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1000000h-100FFFFh 1010000h-101FFFFh 1020000h-102FFFFh 1030000h-103FFFFh 1040000h-104FFFFh 1050000h-105FFFFh 1060000h-106FFFFh 1070000h-107FFFFh 1030000h-108FFFFh 1090000h-109FFFFh 10A0000h-10AFFFFh 10B0000h-10BFFFFh 10C0000h-10CFFFFh 10D0000h-10DFFFFh 10E0000h-10EFFFFh 10F0000h-10FFFFFh 1100000h-110FFFFh 1110000h-111FFFFh 1120000h-112FFFFh 1130000h-113FFFFh 1140000h-114FFFFh 1150000h-115FFFFh 1160000h-116FFFFh 1170000h-117FFFFh 1180000h-118FFFFh 1190000h-119FFFFh 11A0000h-11AFFFFh 11B0000h-11BFFFFh 11C0000h-11CFFFFh 11D0000h-11DFFFFh 11E0000h-11EFFFFh 11F0000h-11FFFFFh Bank 9 Bank Sector SA288 SA289 SA290 SA291 SA292 SA293 SA294 SA295 SA296 SA297 SA298 SA299 SA300 SA301 SA302 SA303 SA304 SA305 SA306 SA307 SA308 SA309 SA310 SA311 SA312 SA313 SA314 SA315 SA316 SA317 SA318 SA319 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1200000h-120FFFFh 1210000h-121FFFFh 1220000h-122FFFFh 1230000h-123FFFFh 1240000h-124FFFFh 1250000h-125FFFFh 1260000h-126FFFFh 1270000h-127FFFFh 1230000h-128FFFFh 1290000h-129FFFFh 12A0000h-12AFFFFh 12B0000h-12BFFFFh 12C0000h-12CFFFFh 12D0000h-12DFFFFh 12E0000h-12EFFFFh 12F0000h-12FFFFFh 1300000h-130FFFFh 1310000h-131FFFFh 1320000h-132FFFFh 1330000h-133FFFFh 1340000h-134FFFFh 1350000h-135FFFFh 1360000h-136FFFFh 1370000h-137FFFFh 1380000h-138FFFFh 1390000h-139FFFFh 13A0000h-13AFFFFh 13B0000h-13BFFFFh 13C0000h-13CFFFFh 13D0000h-13DFFFFh 13E0000h-13EFFFFh 13F0000h-13FFFFFh 18 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 6 of 8) Bank Sector SA320 SA321 SA322 SA323 SA324 SA325 SA326 SA327 SA328 SA329 SA330 SA331 SA332 SA333 SA334 Bank 10 SA335 SA336 SA337 SA338 SA339 SA340 SA341 SA342 SA343 SA344 SA345 SA346 SA347 SA348 SA349 SA350 SA351 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1400000h-140FFFFh 1410000h-141FFFFh 1420000h-142FFFFh 1430000h-143FFFFh 1440000h-144FFFFh 1450000h-145FFFFh 1460000h-146FFFFh 1470000h-147FFFFh 1430000h-148FFFFh 1490000h-149FFFFh 14A0000h-14AFFFFh 14B0000h-14BFFFFh 14C0000h-14CFFFFh 14D0000h-14DFFFFh 14E0000h-14EFFFFh 14F0000h-14FFFFFh 1500000h-150FFFFh 1510000h-151FFFFh 1520000h-152FFFFh 1530000h-153FFFFh 1540000h-154FFFFh 1550000h-155FFFFh 1560000h-156FFFFh 1570000h-157FFFFh 1580000h-158FFFFh 1590000h-159FFFFh 15A0000h-15AFFFFh 15B0000h-15BFFFFh 15C0000h-15CFFFFh 15D0000h-15DFFFFh 15E0000h-15EFFFFh 15F0000h-15FFFFFh Bank 11 Bank Sector SA352 SA353 SA354 SA355 SA356 SA357 SA358 SA359 SA360 SA361 SA362 SA363 SA364 SA365 SA366 SA367 SA368 SA369 SA370 SA371 SA372 SA373 SA374 SA375 SA376 SA377 SA378 SA379 SA380 SA381 SA382 SA383 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 1600000h-160FFFFh 1610000h-161FFFFh 1620000h-162FFFFh 1630000h-163FFFFh 1640000h-164FFFFh 1650000h-165FFFFh 1660000h-166FFFFh 1670000h-167FFFFh 1630000h-168FFFFh 1690000h-169FFFFh 16A0000h-16AFFFFh 16B0000h-16BFFFFh 16C0000h-16CFFFFh 16D0000h-16DFFFFh 16E0000h-16EFFFFh 16F0000h-16FFFFFh 1700000h-170FFFFh 1710000h-171FFFFh 1720000h-172FFFFh 1730000h-173FFFFh 1740000h-174FFFFh 1750000h-175FFFFh 1760000h-176FFFFh 1770000h-177FFFFh 1780000h-178FFFFh 1790000h-179FFFFh 17A0000h-17AFFFFh 17B0000h-17BFFFFh 15C0000h-17CFFFFh 17D0000h-17DFFFFh 17E0000h-17EFFFFh 17F0000h-17FFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 19 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 7 of 8) Bank Sector SA384 SA385 SA386 SA387 SA388 SA389 SA390 SA391 SA392 SA393 SA394 SA395 SA396 SA397 SA398 Bank 12 SA399 SA400 SA401 SA402 SA403 SA404 SA405 SA406 SA407 SA408 SA409 SA410 SA411 SA412 SA413 SA414 SA415 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1800000h-180FFFFh 1810000h-181FFFFh 1820000h-182FFFFh 1830000h-183FFFFh 1840000h-184FFFFh 1850000h-185FFFFh 1860000h-186FFFFh 1870000h-187FFFFh 1830000h-188FFFFh 1890000h-189FFFFh 18A0000h-18AFFFFh 18B0000h-18BFFFFh 18C0000h-18CFFFFh 18D0000h-18DFFFFh 18E0000h-18EFFFFh 18F0000h-18FFFFFh 1900000h-190FFFFh 1910000h-191FFFFh 1920000h-192FFFFh 1930000h-193FFFFh 1940000h-194FFFFh 1950000h-195FFFFh 1960000h-196FFFFh 1970000h-197FFFFh 1980000h-198FFFFh 1990000h-199FFFFh 19A0000h-19AFFFFh 19B0000h-19BFFFFh 19C0000h-19CFFFFh 19D0000h-19DFFFFh 19E0000h-19EFFFFh 19F0000h-19FFFFFh Bank 13 Bank Sector SA416 SA417 SA418 SA419 SA420 SA421 SA422 SA423 SA424 SA425 SA426 SA427 SA428 SA429 SA430 SA431 SA432 SA433 SA434 SA435 SA436 SA437 SA438 SA439 SA440 SA441 SA442 SA443 SA444 SA445 SA446 SA447 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1A00000h-1A0FFFFh 1A10000h-1A1FFFFh 1A20000h-1A2FFFFh 1A30000h-1A3FFFFh 1A40000h-1A4FFFFh 1A50000h-1A5FFFFh 1A60000h-1A6FFFFh 1A70000h-1A7FFFFh 1A30000h-1A8FFFFh 1A90000h-1A9FFFFh 1AA0000h-1AAFFFFh 1AB0000h-1ABFFFFh 1AC0000h-1ACFFFFh 1AD0000h-1ADFFFFh 1AE0000h-1AEFFFFh 1AF0000h-1AFFFFFh 1B00000h-1B0FFFFh 1B10000h-1B1FFFFh 1B20000h-1B2FFFFh 1B30000h-1B3FFFFh 1B40000h-1B4FFFFh 1B50000h-1B5FFFFh 1B60000h-1B6FFFFh 1B70000h-1B7FFFFh 1B80000h-1B8FFFFh 1B90000h-1B9FFFFh 1BA0000h-1BAFFFFh 1BB0000h-1BBFFFFh 1BC0000h-1BCFFFFh 1BD0000h-1BDFFFFh 1BE0000h-1BEFFFFh 1BF0000h-1BFFFFFh 20 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.1 S29NS512P Sector & Memory Address Map (Sheet 8 of 8) Bank Sector SA448 SA449 SA450 SA451 SA452 SA453 SA454 SA455 SA456 SA457 SA458 SA459 SA460 SA461 SA462 Bank 14 SA463 SA464 SA465 SA466 SA467 SA468 SA469 SA470 SA471 SA472 SA473 SA474 SA475 SA476 SA477 SA478 SA479 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 1C00000h-1C0FFFFh 1C10000h-1C1FFFFh 1C20000h-1C2FFFFh 1C30000h-1C3FFFFh 1C40000h-1C4FFFFh 1C50000h-1C5FFFFh 1C60000h-1C6FFFFh 1C70000h-1C7FFFFh 1C30000h-1C8FFFFh 1C90000h-1C9FFFFh 1CA0000h-1CAFFFFh 1CB0000h-1CBFFFFh 1CC0000h-1CCFFFFh 1CD0000h-1CDFFFFh 1CE0000h-1CEFFFFh 1CF0000h-1CFFFFFh 1D00000h-1D0FFFFh 1D10000h-1D1FFFFh 1D20000h-1D2FFFFh 1D30000h-1D3FFFFh 1D40000h-1D4FFFFh 1D50000h-1D5FFFFh 1D60000h-1D6FFFFh 1D70000h-1D7FFFFh 1D80000h-1D8FFFFh 1D90000h-1D9FFFFh 1DA0000h-1DAFFFFh 1DB0000h-1DBFFFFh 1DC0000h-1DCFFFFh 1DD0000h-1DDFFFFh 1DE0000h-1DEFFFFh 1DF0000h-1DFFFFFh Bank 15 Bank Sector SA480 SA481 SA482 SA483 SA484 SA485 SA486 SA487 SA488 SA489 SA490 SA491 SA492 SA493 SA494 SA495 SA496 SA497 SA498 SA499 SA500 SA501 SA502 SA503 SA504 SA505 SA506 SA507 SA508 SA509 SA510 SA511 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 1E00000h-1E0FFFFh 1E10000h-1E1FFFFh 1E20000h-1E2FFFFh 1E30000h-1E3FFFFh 1E40000h-1E4FFFFh 1E50000h-1E5FFFFh 1E60000h-1E6FFFFh 1E70000h-1E7FFFFh 1E30000h-1E8FFFFh 1E90000h-1E9FFFFh 1EA0000h-1EAFFFFh 1EB0000h-1EBFFFFh 1EC0000h-1ECFFFFh 1ED0000h-1EDFFFFh 1EE0000h-1EEFFFFh 1EF0000h-1EFFFFFh 1F00000h-1F0FFFFh 1F10000h-1F1FFFFh 1F20000h-1F2FFFFh 1F30000h-1F3FFFFh 1F40000h-1F4FFFFh 1F50000h-1F5FFFFh 1F60000h-1F6FFFFh 1F70000h-1F7FFFFh 1F80000h-1F8FFFFh 1F90000h-1F9FFFFh 1FA0000h-1FAFFFFh 1FB0000h-1FBFFFFh 1FC0000h-1FCFFFFh 1FD0000h-1FDFFFFh 1FE0000h-1FEFFFFh 1FF0000h-1FFFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 21 Data Sheet (Advance Information) Table 5.2 S29NS256P Sector & Memory Address Map (Sheet 1 of 3) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank 0 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Bank 1 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Bank 4 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh Bank 6 Bank 3 Bank 2 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 22 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.2 S29NS256P Sector & Memory Address Map (Sheet 2 of 3) Bank Sector SA80 SA81 SA82 SA83 SA84 SA85 SA86 Bank 5 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Bank 8 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 Bank 9 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 800000h-80FFFFh 810000h-81FFFFh 820000h-82FFFFh 830000h-83FFFFh 840000h-84FFFFh 850000h-85FFFFh 860000h-86FFFFh 870000h-87FFFFh 880000h-88FFFFh 890000h-89FFFFh 8A0000h-8AFFFFh 8B0000h-8BFFFFh 8C0000h-8CFFFFh 8D0000h-8DFFFFh 8E0000h-8EFFFFh 8F0000h-8FFFFFh 900000h-90FFFFh 910000h-91FFFFh 920000h-92FFFFh 930000h-93FFFFh 940000h-94FFFFh 950000h-95FFFFh 960000h-96FFFFh 970000h-97FFFFh 980000h-98FFFFh 990000h-99FFFFh 9A0000h-9AFFFFh 9B0000h-9BFFFFh 9C0000h-9CFFFFh 9D0000h-9DFFFFh 9E0000h-9EFFFFh 9F0000h-9FFFFFh Bank 11 Bank 10 Bank 7 Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh A00000h-A0FFFFh A10000h-A1FFFFh A20000h-A2FFFFh A30000h-A3FFFFh A40000h-A4FFFFh A50000h-A5FFFFh A60000h-A6FFFFh A70000h-A7FFFFh A80000h-A8FFFFh A90000h-A9FFFFh AA0000h-AAFFFFh AB0000h-ABFFFFh AC0000h-ACFFFFh AD0000h-ADFFFFh AE0000h-AEFFFFh AF0000h-AFFFFFh B00000h-B0FFFFh B10000h-B1FFFFh B20000h-B2FFFFh B30000h-B3FFFFh B40000h-B4FFFFh B50000h-B5FFFFh B60000h-B6FFFFh B70000h-B7FFFFh B80000h-B8FFFFh B90000h-B9FFFFh BA0000h-BAFFFFh BB0000h-BBFFFFh BC0000h-BCFFFFh BD0000h-BDFFFFh BE0000h-BEFFFFh BF0000h-BFFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 23 Data Sheet (Advance Information) Table 5.2 S29NS256P Sector & Memory Address Map (Sheet 3 of 3) Bank Sector SA192 SA193 SA194 SA195 SA196 SA197 SA198 Bank 12 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 Bank 13 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range C00000h-C0FFFFh C10000h-C1FFFFh C20000h-C2FFFFh C30000h-C3FFFFh C40000h-C4FFFFh C50000h-C5FFFFh C60000h-C6FFFFh C70000h-C7FFFFh C80000h-C8FFFFh C90000h-C9FFFFh CA0000h-CAFFFFh CB0000h-CBFFFFh CC0000h-CCFFFFh CD0000h-CDFFFFh CE0000h-CEFFFFh CF0000h-CFFFFFh D00000h-D0FFFFh D10000h-D1FFFFh D20000h-D2FFFFh D30000h-D3FFFFh D40000h-D4FFFFh D50000h-D5FFFFh D60000h-D6FFFFh D70000h-D7FFFFh Bank 15 D80000h-D8FFFFh D90000h-D9FFFFh DA0000h-DAFFFFh DB0000h-DBFFFFh DC0000h-DCFFFFh DD0000h-DDFFFFh DE0000h-DEFFFFh DF0000h-DFFFFFh Bank 14 Bank Sector SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 16 K words 16 K words 16 K words 16 K words Address Range E00000h-E0FFFFh E10000h-E1FFFFh E20000h-E2FFFFh E30000h-E3FFFFh E40000h-E4FFFFh E50000h-E5FFFFh E60000h-E6FFFFh E70000h-E7FFFFh E80000h-E8FFFFh E90000h-E9FFFFh EA0000h-EAFFFFh EB0000h-EBFFFFh EC0000h-ECFFFFh ED0000h-EDFFFFh EE0000h-EEFFFFh EF0000h-EFFFFFh F00000h-F0FFFFh F10000h-F1FFFFh F20000h-F2FFFFh F30000h-F3FFFFh F40000h-F4FFFFh F50000h-F5FFFFh F60000h-F6FFFFh F70000h-F7FFFFh F80000h-F8FFFFh F90000h-F9FFFFh FA0000h-FAFFFFh FB0000h-FBFFFFh FC0000h-FCFFFFh FD0000h-FDFFFFh FE0000h-FEFFFFh FF0000h-FF3FFFh FF4000h-FF7FFFh FF8000h-FFBFFFh FFC000h-FFFFFFh 24 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 5.3 S29NS128P Sector & Memory Address Map (Sheet 1 of 2) Bank Sector SA0 SA1 SA2 Bank 0 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank 2 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 Bank 3 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 Bank 8 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 Bank 9 SA75 SA76 SA77 SA78 SA79 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh Bank 13 Bank 12 Bank 7 Bank 6 Bank 5 Bank 4 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 25 Data Sheet (Advance Information) Table 5.3 S29NS128P Sector & Memory Address Map (Sheet 2 of 2) Bank Sector SA80 SA81 SA82 Bank 10 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 Bank 11 SA91 SA92 SA93 SA94 SA95 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh Bank 15 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh Bank 14 Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 16 K words 16 K words 16 K words 16 K words Address Range 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F3FFFh 7F4000h-7F7FFFh 7F8000h-7FBFFFh 7FC000h-7FFFFFh 26 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 6. Device Operations This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Tables 11.1 and 11.2). The command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. 6.1 Device Operation Table The device must be setup appropriately for each operation. Table 6.1 describes the required state of each control pin for any particular operation. Table 6.1 Device Operations Operation Asynchronous Read - Addresses Latched Asynchronous Write Standby (CE#) Hardware Reset Burst Read Operations Latch Starting Burst Address by CLK L H H L Addr In Addr In X H CE# OE# WE# CLK AVD# Amax- A16 Addr In A/DQ15- A/DQ0 I/O RDY RESET# L L H X H H L H X H X X X X X X X X X Addr In X X I/O HIGH Z HIGH Z H HIGH Z HIGH Z H H Advance Burst read to next address Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle L H X L X X H H H X X H X X X X X I/O HIGH Z HIGH Z H HIGH Z HIGH Z H H L L X H Addr In Addr In X H Legend L = Logic 0, H = Logic 1, X = can be either VIL or VIH., Notes 1. Address is latched on the rising edge of clock. = rising edge, = high to low, = toggle. 2. CLK must stay low or high after CE# goes low when device in Asynchronous Read mode. 6.2 Asynchronous Read All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. To read data from the memory array, the system must first assert a valid address while driving AVD# and CE# to VIL. WE# must remain at VIH. The rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. The data is output on A/DQ15 - A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 27 Data Sheet (Advance Information) 6.3 Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for Asynchronous read and can be automatically enabled for burst mode and the address is latched on the first rising edge of CLK input, while AVD# is held low for one clock cycle. Prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (tIACC) of each burst access, what mode of burst operation is desired and how the RDY signal transitions with valid data. The system would then write the configuration register command sequence. At startup the system writes the Set Configuration Register command sequence to optimize the system performance. The data is output tIACC after the rising edge of the first CLK. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that data is output only at the rising edge of the clock. RDY indicates the initial latency. Note that the device has a fixed internal address boundary that occurs every 128 words. No boundary crossing latency is required when the device operates with wait states set from 2 to 9. 6.3.1 Latency Tables for Variable Wait State Tables 6.2 - 6.9 show the latency for variable wait state in a normal Burst operation. Table 6.2 Address Latency for 9 Wait States Word 0 1 2 3 9 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 Table 6.3 Address Latency for 8 Wait States Word 0 1 2 3 8 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 28 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 6.4 Address Latency for 7 Wait States Word 0 1 2 3 7 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 Table 6.5 Address Latency for 6 Wait States Word 0 1 2 3 6 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 6.6 Address Latency for 5 Wait States Word 0 1 2 3 5 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 1 ws 1 ws 1 ws D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 6.7 Address Latency for 4 Wait States Word 0 1 2 3 4 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 1 ws 1 ws D7 D8 D8 D8 D8 D9 D9 D9 D9 D10 D10 D10 D10 D11 D11 D11 D11 D12 D12 D12 D12 D13 D13 D13 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 29 Data Sheet (Advance Information) Table 6.8 Address Latency for 3 Wait States Word 0 1 2 3 3 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 1 ws D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 D9 D10 D11 D11 D10 D11 D12 D12 D11 D12 D13 D13 D12 D13 D14 D14 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 Table 6.9 Address Latency for 2 Wait States Word 0 1 2 3 2 ws 4 5 6 7 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 D9 D10 D11 D12 D10 D11 D12 D13 D11 D12 D13 D14 D12 D13 D14 D15 Initial Wait D0 D1 D2 D3 D1 D2 D3 D4 D2 D3 D4 D5 D3 D4 D5 D6 D4 D5 D6 D7 D5 D6 D7 D8 D6 D7 D8 D9 D7 D8 D9 D10 D8 D9 D10 D11 30 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 6.1 Synchronous Read Flow Chart Note: Setup Configuration Register parameters Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Set Configuration Registers Command and Settings: Address 555h, Data D0h Address X00h, Data CR0-CR1 Command Cycle CR = Configuration Registers Load Initial Address Address = RA RA = Read Address Wait tIACC + Programmable Wait State Setting CR13-CR11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles Read Initial Data RD = DQ[15:0] RD = Read Data Wait X Clocks: Additional Latency Due to Starting Address, Clock Frequency, and Boundary Crossing Refer to the Latency tables. Read Next Data RD = DQ[15:0] Delay X Clocks Crossing Boundary? No Yes End of Data? Yes Completed 6.3.2 Continuous Burst Read Mode In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wraps around to address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the device. If the address being read crosses a 128-word line boundary within the same bank, but not into a program or erase suspended sector, as mentioned above, additional latency cycles are required as reflected by the configuration register table (Table 6.11) and Tables 6.2 - 6.9 . If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 31 Data Sheet (Advance Information) 6.3.3 8-Word, 16-Word, and 32-Word Linear Burst Read with Wrap Around In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 6.10). For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 38-3Fh, and the burst sequence is 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are read, regardless of where the starting address occurs in the address group, and then terminates the burst read. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. Table 6.10 Burst Address Groups Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words Group Address Ranges 0 - 7h, 8 - Fh, 10 - 17h,... 0 - Fh, 10 - 1Fh, 20 - 2Fh,... 00 - 1Fh, 20 - 3Fh, 40 - 5Fh,... 6.3.4 8-Word, 16-Word, and 32-Word Linear Burst without Wrap Around If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. For example, if the starting address in the 8-word mode is 3Ch, the address range to be read is 3C-43h, and the burst sequence is 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which incurs the additional boundary crossing wait state. 6.3.5 Configuration Registers This device uses two 16-bit configuration registers to set various operational parameters. Upon power-up or hardware reset, the device is capable of the asynchronous read mode and synchronous read, and the configuration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence before attempting burst operations. The Configuration Register can also be read using a command sequence (see Table 11.1). The following list describes the register settings. Table 6.11 Configuration Register CR Bit CR0.15 CR0.14 Function Reserved (Not used) Reserved (Not used) 0 = Reserved (Default) 1 = Reserved 0 = Reserved (Default) 1 = Reserved Settings (Binary) 32 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 6.11 Configuration Register CR Bit CR1.0 0001 0010 CR0.13 0011 0100 CR0.12 0101 Programmable Wait State (Note 1) 0110 = 0111 1000 = 1001 ... CR0.11 initial data is valid on the 8th 9th rising CLK edge AVD# transition to VIH Reserved 7th = initial data is valid on the 3rd 4th 5th 6th rising CLK edge AVD# transition to VIH Function 0000 Settings (Binary) 2nd 1101 1110 = = initial data is valid on the 13th rising CLK edge Reserved AVD# transition to VIH (Default) 1111 CR0.10 CR0.9 CR0.8 CR0.7 CR0.6 CR0.5 CR1.4 CR0.4 CR0.3 RDY Polarity Reserved (Not used) RDY Reserved (Not used) Reserved (Not used) Reserved (Not used) Output Drive Strength RDY Function Burst Wrap Around 0 = RDY signal is active low 1 = RDY signal is active high (Default) 0 = Reserved 1 = Reserved (Default) 0 = RDY active one clock cycle before data 1 = RDY active with data (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved 1 = Reserved (Default) 0 = Reserved (Default) 1 = Reserved 0 = Full Drive= Current Driver Strength (Default) 1 = Half Drive 0 = RDY (Default) 1 = Reserved 0 = No Wrap Around Burst 1 = Wrap Around Burst (Default) 000 = Continuous (Default) CR0.2 010 = 8-Word Linear Burst CR0.1 CR0.0 Burst Length 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes 1. The addresses are latched by rising edge of CLK. 2. CR1.0 to CR1.3 and CR1.5 to CR1.15 = 1 (Default). 3. A software reset command is required after read command. 4. CR0.3 is ignored if in continuous read mode (no wrap around). 6.4 Autoselect The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes can also be accessed in the system. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 6.12). The remaining address bits are don't care. The most significant four bits of the address during the third write cycle select the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data read without exiting the Autoselect mode. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 33 Data Sheet (Advance Information) To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support simultaneous operations or burst mode. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). See Table 11.1 for command sequence details. Table 6.12 Autoselect Addresses Description Manufacturer ID Byte 00 Device ID, Byte 01 Sector Lock/Unlock Byte 02 Address (BA) + 00h 0001h 307Eh(NS512P) 317Eh(NS256P) 327Eh(NS128P) 0001h = Locked, 0000h = Unlocked DQ15 - DQ8 = reserved DQ7 - Factory Lock Bit; 1 = Locked, 0 = Not Locked DQ6 - Customer Lock Bit; 1 = Locked, 0 = Not Locked Indicator Bits Byte 07 (BA) + 07h DQ5 - Handshake Bit; 1 = Reserved, 0 = Standard Handshake DQ4 and DQ3 - WP# Protection Boot Code; 01 = WP# Protects Top Boot Sectors, DQ2 - DQ0 = reserved Device ID, Byte 0E Device ID, Byte 0F (BA) + 0Eh 303Fh (NS512P) 3141h (NS256P) 3243h (NS128P) 3000h (NS512P) 3100h (NS256P) 3200h (NS128P) Read Data (BA) + 01h (SA) + 02h (BA) + 0Fh Software Functions and Sample Code Table 6.13 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write Byte Address BA+AAAh BA+555h BA+AAAh Word Address BA+555h BA+2AAh BA+555h Data 0x00AAh 0x0055h 0x0090h Table 6.14 Autoselect Exit (LLD Function = lld_AutoselectExitCmd) Cycle Unlock Cycle 1 Notes 1. Any offset within the device works. 2. BA = Bank Address. The bank address is required. 3. base = base address. Operation Write Byte Address base + xxxxh Word Address base + xxxxh Data 0x00F0h The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. 34 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) /* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */ /* Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ 6.5 Program/Erase Operations These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. However, prior to any programming and or erase operation, devices can be setup appropriately as outlined in the configuration register (Table 6.11). For any program and or erase operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or programming data. All addresses are latched on the rising edge of AVD# or falling edge of WE#, and all data is latched on the first rising edge of WE#. Note the following: When the Embedded Program/Erase algorithm is complete, the device returns to the read mode. The system can determine the status of the Program/Erase operation. Refer to the Write Operation Status section for further information. While 1 can be programmed to 0, a 0 cannot be programmed to a 1. Any such attempt is ignored as only an erase operation can covert a 0 to a 1. Any commands written to the device during the Embedded Program/Erase Algorithm are ignored except the Program/Erase Suspend command. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset or power removal immediately terminates the Program/Erase operation and the Program/ Erase command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries only for single word programming operation. See Write Buffer Programming when using the write buffer. Note: The system may also lock or unlock any sector while the erase operation is suspended. 6.5.1 Single Word Programming Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to program an individual Flash address. While the single word programming method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 11.1 for the required bus cycles and Figure 6.2 for the flowchart. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 35 Data Sheet (Advance Information) When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Figure 6.2 Single Word Program Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command: Address 555h, Data A0h Setup Command Program Data to Address: PA, PD Program Address (PA), Program Data (PD) Perform Polling Algorithm (see Write Operation Status flowchart) Polling Status = Busy? No Yes Polling Status = Complete? No Yes Error condition (Exceeded Timing Limits) Operation successfully completed Operation failed Software Functions and Sample Code Table 6.15 Single Word Program (LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. 36 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) /* Example: Program Command */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)pa ) /* Poll for program completion */ = = = = 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */ 6.5.2 Write Buffer Programming Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of word locations minus 1 that is loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Note: the size of the write buffer is dependent upon which data are being loaded. Also note that the number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must be in sequential order. The write-buffer addresses must be in the same sector for all address/data pairs loaded into the write buffer. It is to be noted that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer addresses, the operation aborts after the Write to Buffer command is executed. Also, the starting address must be the least significant address and must be incremental and that the write buffer data cannot be in different sectors. After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations must be loaded in sequential order starting with the lowest address in the page. Note that if the number of address/data pairs do not match the word count, the program buffer to flash command is ignored. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter decrements for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. The Write Buffer Programming Sequence is ABORTED in the following ways: Load a value that is greater than the buffer size during the Number of Locations to Program step (DQ7 is not valid in this condition). Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 37 Data Sheet (Advance Information) Software Functions and Sample Code Table 6.16 Write Buffer Program (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Word Address Base + 555h Base + 2AAh Data 00AAh 0055h 0025h Word Count (N-1)h Program Address Program Address Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last Load Buffer Word N Write Buffer to Flash Write Write Program Address, Word N Sector Address Word N 0029h Notes 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same write buffer. */ /* A write buffer begins at addresses evenly divisible */ /* by 0x20. UINT16 i; */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)dst ) = 0x0025; /* write write buffer load command */ *( (UINT16 *)dst ) = wc; /* write word count (minus 1) */ for (i=0;i<=wc;i++) { *dst++ = *src++; /* ALL dst MUST BE in same Write Buffer */ } *( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* Example: Write Buffer Abort Reset */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */ *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */ *( (UINT16 *)base_addr + 0x555 ) = 0x00F0; /* write buffer abort reset */ 38 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 6.3 Write Buffer Programming Operation Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Issue Write Buffer Load Command: Program Address Data 25h Load Word Count to Program Program Data to Address: SA = wc wc = number of words - 1 Yes wc = 0? Confirm command: SA 29h No Write Next Word, Decrement wc: PA data , wc = wc - 1 Perform Polling Algorithm (see Write Operation Status flowchart) Polling Status = Done? No No Yes Error? Yes Write Buffer Abort? No Yes RESET. Issue Write Buffer Abort Reset Command FAIL. Issue reset command to return to read array mode. PASS. Device is in read mode. 6.5.3 Sector Erase The sector erase function erases one or more sectors in the memory array. (See Table 11.1 and Figure 6.4.) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the timeout period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 39 Data Sheet (Advance Information) to determine if the sector erase timer has timed out (See the section, DQ3: Sector Erase Timeout State Indicator.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 6.4 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations for parameters and timing diagrams. Software Functions and Sample Code Table 6.17 Sector Erase (LLD Function = lld_SectorEraseCmd) Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Sector Erase Command Operation Write Write Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Sector Address Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address Data 00AAh 0055h 0080h 00AAh 0055h 0030h Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA. The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Sector Erase Command *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x555 *( (UINT16 *)base_addr + 0x2AA *( (UINT16 *)sector_address ) */ )= )= )= )= )= = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0030; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ sector erase command */ 40 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 6.4 Sector Erase Operation Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure No Select Additional Sectors? Yes Write Additional Sector Addresses * Each additional cycle must be written within tSEA timeout * Timeout resets after each additional cycle is written * The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands No Poll DQ3. DQ3 = 1? Yes Yes Last Sector Selected? No * No limit on number of sectors * Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data Perform Write Operation Status Algorithm Status may be obtained by reading DQ7, DQ6 and/or DQ2. Yes Done? No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits) PASS. Device returns to reading array. FAIL. Write reset command to return to reading array. Notes 1. See Table 11.1 for erase command sequence. 2. See DQ3: Sector Erase Timeout State Indicator for information on the sector erase timeout. 6.5.4 Chip Erase Command Sequence Chip erase is a six-bus cycle operation as indicated by Table 11.1. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. Table 11.1 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these status bits. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 41 Data Sheet (Advance Information) Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Software Functions and Sample Code Table 6.18 Chip Erase (LLD Function = lld_ChipEraseCmd) Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command Operation Write Write Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0080h 00AAh 0055h 0010h The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.comm) for general information on Spansion Flash memory software development guidelines. /* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x000 ) = = = = = = 0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0010; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ chip erase command */ 6.5.5 Erase Suspend/Erase Resume Commands When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written after the tSEA time-out period has expired and during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 6.27 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to the Write Buffer Programming section and the Autoselect section for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: While an erase operation can be suspended and resumed multiple times, a minimum delay of tERS (Erase Resume to Suspend) is required from resume to the next suspend. 42 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Software Functions and Sample Code Table 6.19 Erase Suspend (LLD Function = lld_EraseSuspendCmd) Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 00B0h The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase suspend command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */ Table 6.20 Erase Resume (LLD Function = lld_EraseResumeCmd) Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 0030h The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase resume command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command /* The flash needs adequate time in the resume state */ */ 6.5.6 Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. Addresses are don't-cares when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See the Autoselect section for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See the Write Operation Status section for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. Note: While a program operation can be suspended and resumed multiple times, a minimum delay of tPRS (Program Resume to Suspend) is required from resume to the next suspend. Software Functions and Sample Code Table 6.21 Program Suspend (LLD Function = lld_ProgramSuspendCmd) Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 00B0h February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 43 Data Sheet (Advance Information) The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program suspend command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */ Table 6.22 Program Resume (LLD Function = lld_ProgramResumeCmd) Cycle 1 Operation Write Byte Address Bank Address Word Address Bank Address Data 0030h The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Program resume command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 6.5.7 Accelerated Program/Sector Erase Accelerated single word programming, write buffer programming and sector erase, operations are enabled through the VPP function. This method is faster than the standard chip program and erase command sequences. The accelerated chip program and erase functions must not be used more than 100 times per sector. In addition, accelerated chip program and erase should be performed at room temperature (30C 10C). If the system asserts VHH on this input, the device automatically enters the accelerated mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the VPP input, upon completion of the embedded program or erase operation, returns the device to normal operation. Sectors must be unlocked prior to raising VPP to VHH. The VPP pin must not be at VHH for operations other than accelerated programming and accelerated sector erase, or device damage may result. The VPP pin must not be left floating or unconnected; inconsistent behavior of the device may result. VPP locks all sector if set to VIL; VPP should be set to VIH for all other conditions. 6.5.8 Unlock Bypass The unlock bypass feature allows the system to primarily program to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 11.1 shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain 44 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the VPP input. When the system asserts VHH on this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the VPP input to accelerate the operation. Refer to the Erase/Program Timing section for parameters, and Figures 10.12 and 10.13 for timing diagrams Software Functions and Sample Code The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. Table 6.23 Unlock Bypass Entry (LLD Function = lld_UnlockBypassEntryCmd) Cycle 1 2 3 Description Unlock Unlock Entry Command Operation Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0020h /* Example: Unlock Bypass Entry Command */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock *( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock *( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock /* At this point, programming only takes two write cycles. /* Once you enter Unlock Bypass Mode, do a series of like /* operations (programming or sector erase) and then exit /* Unlock Bypass Mode before beginning a different type of /* operations. cycle 1 cycle 2 bypass command */ */ */ */ */ */ */ */ Table 6.24 Unlock Bypass Program (LLD Function = lld_UnlockBypassProgramCmd) Cycle 1 2 Description Program Setup Command Program Command Operation Write Write Byte Address Base + xxxh Program Address Word Address Base +xxxh Program Address Data 00A0h Program Data /* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; *( (UINT16 *)pa ) = data; /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */ /* write program setup command /* write data to be programmed */ */ Table 6.25 Unlock Bypass Reset (LLD Function = lld_UnlockBypassResetCmd) Cycle 1 2 Description Reset Cycle 1 Reset Cycle 2 Operation Write Write Byte Address Base + xxxh Base + xxxh Word Address Base +xxxh Base +xxxh Data 0090h 0000h /* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000; February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 45 Data Sheet (Advance Information) 6.5.9 Write Operation Status The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. Similarly, attempting to program 1 over a 0 does not return valid Date# information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ1 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ1 may be still invalid. Valid data on DQ7-D01 appears on successive read cycles. See the following for more information: Table 6.27, Write Operation Status, shows the outputs for Data# Polling on DQ7. Table 6.5, Write Operation Status Flowchart, shows the Data# Polling algorithm; and Figure 10.15, Data# Polling Timings (During Embedded Algorithm), shows the Data# Polling timing diagram. 46 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 6.5 Write Operation Status Flowchart START Read 1 (Note 6) DQ7=valid data? NO YES Erase Operation Complete YES Read 1 DQ5=1? NO Read 2 Read3= valid data? YES NO Read 3 Read 2 YES Write Buffer Programming? Program Operation Failed YES NO Read 3 Device BUSY, Re-Poll Programming Operation? NO (Note 3) (Note 1) DQ6 toggling? YES TIMEOUT (Note 1) DQ6 toggling? NO (Note 2) (Note 5) YES DEVICE ERROR (Note 4) Read3 DQ1=1? YES NO YES DQ2 toggling? NO NO Device BUSY, Re-Poll Read 2 Device BUSY, Re-Poll Erase Operation Complete Read 3 Device in Erase/Suspend Mode Read3 DQ1=1 AND DQ7 ? Valid Data? YES Write Buffer Operation Failed NO Notes: 1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3) May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4) Write buffer error if DQ1 of last read =1. 5) Invalid state, use RESET command to exit operation. 6) Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) Data polling algorithm valid for all operations except advanced sector protection. 8) It can fail if one tries to program DQ7 from '0' to '1' Device BUSY, Re-Poll DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 47 Data Sheet (Advance Information) The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See the following for additional information: Figure 6.5, Write Operation Status Flowchart; Figure 10.16, Toggle Bit Timings (During Embedded Algorithm), and Tables 6.26 and 6.27. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state DQ2: Toggle Bit II The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6.26 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 6.5, the DQ6: Toggle Bit I section, and Figures 10.15 - 10.18. Table 6.26 DQ6 and DQ2 Indications If device is programming, actively erasing, and the system reads any address at the bank being programmed at an address within a sector selected for erasure, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, erase suspended, programming in erase suspend at an address within sectors not selected for erasure, any address at the bank being programmed then DQ6 toggles, toggles, toggles, does not toggle, returns array data, toggles, and DQ2 does not toggle. also toggles. does not toggle. toggles. returns array data. The system can read from any sector not selected for erasure. is not applicable. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 - DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system notes and stores the value of the toggle bit after the first read. After the second read, the system compares the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7 - DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 6.5 for more details. Note: When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and DQ2 toggle between high and low states in a series of consecutive and contiguous status read cycles. In order for this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. If it is not possible to temporarily prevent reads to 48 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) other memory banks, then it is recommended to use the DQ7 status bit as the alternative method of determining the active or inactive status of the write operation. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the system must write the reset command to return to the read mode (or to the erasesuspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timeout State Indicator After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See the Sector Erase Command Sequence, for more details. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 6.27 shows the status of DQ3 relative to the other status bits. DQ1: Write to Buffer Abort DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details. Table 6.27 Write Operation Status Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Program Suspended Sector Reading within Non-Program Suspended Sector Erase Suspended Sector Non-Erase Suspended Sector DQ7 (2) DQ7# 0 INVALID (Not Allowed) Data DQ6 Toggle Toggle INVALID (Not Allowed) Data DQ5 (1) 0 0 INVALID (Not Allowed) Data DQ3 N/A 1 INVALID (Not Allowed) Data DQ2 (2) No toggle Toggle INVALID (Not Allowed) Data DQ1 (4) 0 N/A INVALID (Not Allowed) Data Program Suspend Mode (3) 1 No toggle 0 N/A Toggle N/A Erase Suspend Mode Erase-SuspendRead Data DQ7# DQ7# DQ7# DQ7# Data Toggle Toggle Toggle Toggle Data 0 0 1 0 Data N/A N/A N/A N/A Data N/A N/A N/A N/A Data N/A 0 0 1 Erase-Suspend-Program Write to Buffer (5) BUSY State Exceeded Timing Limits ABORT State Notes 1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. Data are invalid for addresses in a Program Suspended sector. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 49 Data Sheet (Advance Information) 6.6 Simultaneous Read/Write The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 10.21, Back-to-Back Read/Write Cycle Timings, shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specification. 6.7 Writing Commands/Command Sequences When the device is in Asynchronous read, only Asynchronous write operations are allowed. During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the rising edge of AVD#, while data is latched on the rising edge of WE#. An erase operation can erase one sector, multiple sectors, or the entire device. Table 5.1 - Table 5.3 indicate the address space that each sector occupies. The device address space is divided into sixteen banks: for NS512P, all 16 banks contain 64-Kword sectors while for NS256P and NS128P, Banks 0 through 14 contain only 64 Kword sectors, Bank 15 contains 16-Kword boot sectors in addition to 64 Kword sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to uniquely select a sector. ICC2 in the DC Characteristics section represents the active current specification for the write mode. AC Characteristics-Synchronous and AC Characteristics-Asynchronous contain timing specification tables and timing diagrams for write operations. 6.8 Handshaking The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY pin which is a dedicated output and is controlled by CE#. 6.9 Hardware Reset The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. See Figures 10.5 and 10.11 for timing diagrams. 6.10 Software Reset Software reset is part of the command set (see Table 11.1) that also returns the device to array read mode and must be used for the following conditions: 1. to exit Autoselect mode 2. when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode. 5. after any aborted operations 6. exiting read configuration registration Mode 50 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Software Functions and Sample Code Table 6.28 Reset (LLD Function = lld_ResetCmd) Cycle Reset Command Note Base = Base Address. Operation Write Byte Address Base + xxxh Word Address Base + xxxh Data 00F0h The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; The following are additional points to consider when using the reset command: This command resets the banks to the read and address bits are ignored. Reset commands are ignored once erasure has begun until the operation is complete. Once programming begins, the device ignores reset commands until the operation is complete The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command may be also written during an Autoselect command sequence. If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ1 goes high during a Write Buffer Programming operation, the system must write the Write to Buffer Abort Reset command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table for details]. 6.11 Programmable Output Slew Rate Control This feature allows the user to change the output slew rate during a read operation by setting the configuration register bit CR1.4. It allows 2 programmable slew rates. This feature is for users who do not want to run the part at its maximum speed and could live with a slower output slew rate thereby reducing noise variations at the output. Table 6.29 Programmable Output Slew Rate Mode 1 2 Description Full Drive (Default) Half Drive IOL & IOH 100 A 50 A February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 51 Data Sheet (Advance Information) 7. Advanced Sector Protection/Unprotection The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 7.1. Figure 7.1 Advanced Sector Protection/Unprotection Hardware Methods Software Methods Lock Register (One Time Programmable) VPP = VIL (All sectors locked) Password Method (DQ2) Persistent Method (DQ1) (All boot sectors locked) WP# = VIL 64-bit Password (One Time Protect) PPB Lock Bit1,2,3 0 = PPBs Locked 1 = PPBs Unlocked 1. Bit is volatile, and defaults to 1 on reset. 2. Programming to 0 locks all PPBs to their current state. 3. Once programmed to 0, requires hardware reset to unlock. Memory Array Sector 0 Sector 1 Sector 2 Persistent Protection Bit (PPB)4,5 PPB 0 PPB 1 PPB 2 Dynamic Protection Bit (DYB)6,7,8 DYB 0 DYB 1 DYB 2 Sector N-2 Sector N-1 Sector N 3 PPB N-2 PPB N-1 PPB N 4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively DYB N-2 DYB N-1 DYB N 6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is 1 (unprotected). 8. Volatile Bits: defaults to protected after power up. 3. N = Highest Address Sector. 7.1 Lock Register The Lock Register consists of 5 bits. The Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, Password Protection Mode Lock Bit is DQ2, Persistent Sector Protection OTP bit is DQ3 and Volatile Sector Protection Boot bit is DQ4. If DQ0 is 0, it means that the Customer Secured Silicon area is locked and if DQ0 is 1, it means that it is unlocked. When DQ2 is set to 1 and DQ1 is set to 0, the 52 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) device can only be used in the Persistent Protection Mode. When the device is set to Password Protection Mode, DQ1 is required to be set to 1 and DQ2 is required to be set to 0. DQ3 is programmed in the Spansion factory. When the device is programmed to disable all PPB erase command, DQ3 outputs a 0, when the lock register bits are read. Similarly, if the device is programmed to enable all PPB erase command, DQ3 outputs a 1 when the lock register bits are read. Likewise the DQ4 bit is also programmed in the Spansion Factory. DQ4 is the bit which indicates whether Volatile Sector Protection Bit (DYB) is protected or not after boot up. When the device is programmed to set all Volatile Sector Protection Bit protected after power up, DQ4 outputs a 0 when the lock register bits are read. Similarly, when the device is programmed to set all Volatile Sector Protection Bit unprotected after power up, DQ4 outputs a 1. Each of these bits in the lock register are non-volatile. DQ15 - DQ5 are reserved and are 1s. Lock Register DQ15-5 DQ4 DYB Lock Boot Bit 1s 0 = DYB bits power up protected (Default) 1 = DYB bits power up unprotected DQ3 PPB One Time Programmable Bit 0 = All PPB Erase Command disabled 1 = All PPB Erase Command enabled Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Secured Silicon Sector Protection Bit DQ2 DQ1 DQ0 For programming lock register bits refer to Table 11.2. Notes 1. If the password mode is chosen, the password must be programmed and verified before setting the corresponding lock register bit. 2. It is recommended that a sector protection method to be chosen by programming DQ1 or DQ2 prior to shipment 3. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 4. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 5. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. 6. During erase/program suspend, ASP entry commands are not allowed. 7. Data Polling can be done immediately after the lock register programming command sequence (no delay required). Note that status polling can be done only in bank 0. 8. Reads from other banks (simultaneous operation) are not allowed during lock register programming. This restriction applies to both synchronous and asynchronous read operations. After selecting a sector protection method, each sector can operate in any of the following three states: 1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. 2. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Sections 7.2 - 7.6. 7.2 Persistent Protection Bits The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 53 Data Sheet (Advance Information) Notes 1. Each PPB is individually programmed and all are erased in parallel. 2. While programming PPB for a sector, array data can be read from any other bank, except Bank 0 (used for Data# Polling) and the bank in which sector PPB is being programmed. 3. Entry command disables reads and writes for the bank selected. 4. Reads within that bank return the PPB status for that sector. 5. Reads from other banks are allowed while writes are not allowed. 6. All Reads must be performed using the Asynchronous mode. 7. The specific sector address (Amax - A14) are written at the same time as the program command. 8. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and time out without programming or erasing the PPB. 9. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 10. PPB exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0 11. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in Figure 7.2. 12. During PPB program/erase data polling can be done synchronously. 13. If customers attempt to program or erase a protected sector, the device ignores the command and returns to read mode. 54 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 7.2 PPB Program/Erase Algorithm Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA Read Byte Twice Addr = SA0 DQ6 = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice Addr = SA0 Wait 500 s DQ6 = Toggle? Yes No Read Byte. Addr = SA No DQ0 = '1' (Erase) '0' (Pgm.)? Yes FAIL PASS Exit PPB Command Set 7.3 Dynamic Protection Bits Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 55 Data Sheet (Advance Information) Notes 1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. 2. When the parts are first shipped, the DYBs are set and programmed to 0 upon power up or reset. 3. The default state of DYB is protected after power up and all sectors can be modified depending on the status of PPB bit for that sector, (erased to 1). Then the sectors can be modified depending upon the PPB state of that sector (see Table 7.1). 4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. 7. Data polling is not available for DYB program/erase. 8. DYB read data can be done synchronously. 9. If customers attempt to program or erase a protected sector, the device ignores the command and returns to read mode. 7.4 Persistent Protection Bit Lock Bit The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to 0), it locks all PPBs and when cleared (programmed to 1), allows the PPBs to be changed. There is only one PPB Lock Bit per device. Notes 1. If the password mode is chosen, then the password must be programmed and verified before setting the corresponding lock register bit. 2. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power up clears this bit. 3. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings. 7.5 Password Protection Method The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. 2. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time out with the cell as a 0. 3. The password is all 1s when shipped from the factory. 4. All 64-bit password combinations are valid as a password. 5. There is no means to verify what the password is after it is set. 6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 56 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 7. The Password Mode Lock Bit is not erasable. 8. The lower two address bits (A1 - A0) are valid during the Password Read, Password Program, and Password Unlock. 9. The exact password must be entered in order for the unlocking function to occur. 10. The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. Password verification is only allowed during the password programming operation. 13. All further commands to the password region are disabled and all operations are ignored. 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 57 Data Sheet (Advance Information) Figure 7.3 Lock Register Program Algorithm Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Enter Lock Register Command: Address 555h, Data 40h Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD XXXh = Address don't care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once. Wait 4 s (recommended) Perform Polling Algorithm (see Write Operation Status flowchart) Yes Done? No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits) PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. FAIL. Write rest command to return to reading array. 7.6 Advanced Sector Protection Software Examples Table 7.1 Sector Protection Schemes Unique Device PPB Lock Bit 0 = locked 1 = unlocked Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector 0 0 0 0 1 1 1 1 Sector PPB 0 = protected 1 = unprotected 0 0 1 1 0 0 1 1 Sector DYB 0 = protected 1 = unprotected x x 1 0 x x 0 1 Sector Protection Status Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected 58 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 7.1 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. 7.7 Hardware Data Protection Methods The device offers two main types of data protection at the sector level via hardware control: When WP# is at VIL, the highest two sectors are locked (device specific). When VPP is at VIL, all sectors are locked. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods: WP# Method The Write Protect feature provides a hardware method of protecting the highest two sectors (NS256P and NS128P). This function is provided by the WP# pin and overrides the previously discussed Sector Protection/ Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the highest two sectors (NS256P and NS128P) as well as Secured Silicon Area. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP# pin must be held stable during a command sequence execution VPP Method This method is similar to above, except it protects all sectors (including the Secured Silicon Area). Once VPP input is set to VIL, all program and erase functions are disabled and hence all sectors are protected. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse Glitch Protection Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power up. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 59 Data Sheet (Advance Information) 8. 8.1 Power Conservation Modes Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics section represents the standby current specification 8.2 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a new burst operation is required to provide new data. ICC6 in the DC Characteristics section represents the automatic sleep mode current specification. 8.3 Hardware RESET# Input Operation The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset also resets the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. 8.4 Output Disable (OE#) When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. 60 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 9. Secured Silicon Sector Flash Memory Region The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. Please note the following general conditions: While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads can be performed in the Asynchronous or Synchronous mode. Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h. Reads outside of sector 0 return memory array data. Continuous burst read past the maximum address is undefined. Sector 0 is remapped from memory array to Secured Silicon Sector array. Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. Table 9.1 Secured Silicon SectorSecure Sector Addresses Sector Customer Factory Sector Size 128 words 128 words Address Range 000080h-0000FFh 000000h-00007Fh 9.1 Factory Secured Silicon Sector The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: A random, 8 Word secure ESN only within the Factory Secured Silicon Sector Customer code within the Customer Secured Silicon Sector through the SpansionTM programming service. Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services. 9.2 Customer Secured Silicon Sector The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to 1. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 61 Data Sheet (Advance Information) The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. The accelerated programming (VPP) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but reading in Banks 1 through 15 is available. Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0. 9.3 Secured Silicon Sector Entry and Exit Command Sequences The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See Command Definition Table [Secured Silicon Sector Command Table, Appendix Table 11.1 for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read customer and factory Secured Silicon areas Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. Software Functions and Sample Code The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. Table 9.2 Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle Note Base = Base Address. Operation Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0088h /* Example: Secured Silicon Sector *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) Cmd */ Entry Command */ = 0x00AA; /* write unlock cycle 1 */ = 0x0055; /* write unlock cycle 2 */ = 0x0088; /* write Secured Silicon Sector Entry Table 9.3 Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Note Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Word Address Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word 62 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) /* Once in the Secured Silicon Sector mode, you program */ /* words using the programming algorithm. */ Table 9.4 Secured Silicon Sector Exit (LLD Function = lld_SecSiSectorExitCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle 3 Exit Cycle 4 Note Base = Base Address. Operation Write Write Write Write Byte Address Base + AAAh Base + 554h Base + AAAh Any address Word Address Base + 555h Base + 2AAh Base + 555h Any address Data 00AAh 0055h 0090h 0000h /* Example: Secured Silicon Sector *( (UINT16 *)base_addr + 0x555 ) *( (UINT16 *)base_addr + 0x2AA ) *( (UINT16 *)base_addr + 0x555 ) cycle 3 */ *( (UINT16 *)base_addr + 0x000 ) cycle 4 */ Exit Command */ = 0x00AA; /* write unlock cycle 1 */ = 0x0055; /* write unlock cycle 2 */ = 0x0090; /* write Secured Silicon Sector Exit = 0x0000; /* write Secured Silicon Sector Exit February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 63 Data Sheet (Advance Information) 10. Electrical Specifications 10.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground: All Inputs and I/Os except as noted below (1) VCC (1) VPP (2) Output Short Circuit Current (3) -65C to +150C -65C to +125C -0.5 V to + 2.5 V -0.5 V to +2.5 V -0.5 V to +9.5 V 100 mA Notes 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 10.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 10.2. 2. Minimum DC input voltage on pin VPP is -0.5V. During voltage transitions, VPP may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 10.1. Maximum DC voltage on pin VPP is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Figure 10.1 Maximum Negative Overshoot Waveform 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns Figure 10.2 Maximum Positive Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 10.2 Operating Ranges Wireless (I) Devices Ambient Temperature (TA) Supply Voltages VCC Supply Voltages Note Operating ranges define those limits between which the functionality of the device is guaranteed. +1.70 V to +1.95 V -25C to +85C 64 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 10.3 DC Characteristics CMOS Compatible Table 10.1 DC Characteristics--CMOS Compatible Parameter ILI ILO Description Input Load Current Output Leakage Current Test Conditions (1) VIN = VSS to VCC, VCC = VCCmax VOUT = VSS to VCC, VCC = VCCmax CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 32 CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous 108 Mhz 83 Mhz 66 Mhz 108 Mhz 83 Mhz 66 Mhz 108 Mhz 83 Mhz 66 Mhz 108 Mhz 83 Mhz 66 Mhz 10 MHz ICC1 VCC Active Asynchronous Read Current (2) CE# = VIL, OE# = VIH, WE# = VIH CE# = VIL, OE# = VIH, VPP = VIH CE# = RESET# = VCC 0.2 V RESET# = VIL, CLK = VIL CE# = VIL, OE# = VIH, VPP = VIH, (7) CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH, VPP = 9.5 V VPP VCC -0.2 VCC - 0.4 IOL = 100 A, VCC = VCC min = VCC IOH = -100 A, VCC = VCC min VCC - 0.1 8.5 9.5 1.4 5 MHz 1 MHz ICC2 VCC Active Write Current (3) VPP VCC VPP VCC 33 26 24 30 26 24 25 28 26 32 30 28 40 20 10 1 <20 1 20 150 50 5 <7 <15 Min Typ Max 1 1 44 36 33 40 38 35 33 40 37 44 42 39 80 40 20 5 <40 5 70 250 60 40 <10 <20 0.4 VCC + 0.4 0.1 V V V V Unit A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A mA A A A mA A mA mA V 10.3.1 ICC3 ICC4 ICC5 ICC6 IPPW VIL VIH VOL VOH VHH VLKO VCC Standby Current (4) VCC Reset Current VCC Active Current (Read While Write) VCC Sleep Current Accelerated Program Current (5) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage Notes 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 5. Total current during accelerated programming is the sum of VPP and VCC currents. 6. VCCQ = VCC during all ICC measurements. 7. Clock frequency 66 Mhz and in Continuous Mode. 8. For ICC6, when VIH = VIO, VIL = VSS. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 65 Data Sheet (Advance Information) 10.4 Test Conditions Figure 10.3 Test Setup Device Under Test CL Table 10.2 Test Specifications Test Condition Output Load Capacitance, CL, (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels All Speed Options 30 1.0 - 1.50 0.0 - VCC VCC/2 VCCQ/2 Unit pF ns V V V 10.5 Key to Switching Waveforms Waveform Inputs Steady Outputs Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 10.6 Switching Waveforms Figure 10.4 Input Waveforms and Measurement Levels All Inputs and Outputs VCC 0.0 V Input VCC/2 Measurement Level VCCQ/2 Output Table 10.3 VCC Power-Up with No Ramp Rate Restriction Parameter tVCS tRH Description VCC Setup Time Time between RESET# (high) and CE# (low) Test Setup Min Min Time 30 200 Unit s ns Note VCC and VCCQ must be ramped simultaneously for proper power-up. 66 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 10.5 VCC Power-Up Diagram tVCS VCC VCC min VIH RESET# tRH CE# 10.7 CLK Characterization Table 10.4 CLK Characterization Parameter Description Max fCLK CLK Frequency Min 66 MHz 66 83 MHz 83 108 MHz 108 Unit MHz 60 KHz in 8 word Burst, 120 KHz in 16 word Burst, 250 KHz in 32 word Burst, 1 MHz in Continuous Mode 15.1 12.5 0.40 tCLK 0.60 tCLK 3.0 2.5 1.5 ns 9.26 ns ns tCLK tCL/tCH tCR tCF CLK Period CLK Low/High Time Min Min Max CLK Rise Time Max CLK Fall Time Figure 10.6 CLK Characterization tCLK tCH tCL CLK tCR tCF 10.8 AC Characteristics Synchronous/Burst Read Table 10.5 Synchronous/Burst Read Parameter Description JEDEC Standard tIACC tBACC tACS tACH tBDH tRDY Synchronous Access Time Burst Access Time Valid Clock to Output Delay Address Setup Time to CLK (1) Address Hold Time from CLK (1) Data Hold Time Chip Enable to RDY Active Max Max Min Min Min Max 6 3 11.2 80 9 4 5 3 10 5 2 7.6 ns ns ns ns ns ns 66 MHz 83 MHz 108 MHz Unit 10.8.1 February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 67 Data Sheet (Advance Information) Table 10.5 Synchronous/Burst Read Parameter Description JEDEC Standard tOE tCEZ tOEZ tCES tRACC tCAS tAVDS tAVDH tAVD0 tAVD Output Enable to RDY Low Chip Enable to High Z Output Enable to High Z CE# Setup Time to CLK Ready Access Time from CLK CE# Setup Time to AVD# AVD# Low to CLK Setup Time AVD# Hold Time to CLK AVD# High to OE# Low AVD# Pulse Max Max Max Min Max Min Min Min Min Min 11.2 9 10 10 9 10 10 4 9 0 5 3 0 6 7.5 9 10 10 ns ns ns ns ns ns ns ns ns ns 66 MHz 83 MHz 108 MHz Unit Notes 1. Addresses are latched on the rising edge of CLK 2. Synchronous Access Time is calculated using the formula (#of WS - 1)*(clock period) + (tBACC or Clock to Out) 3. Not 100% tested for tCEZ, tOEZ. Table 10.6 Synchronous Wait State Requirements Max Frequency Frequency 14 MHz 14 < Frequency 27MHz 27 MHz < Frequency 40 MHz 40 MHz < Frequency 54 MHz 54 MHz < Frequency 66 MHz 66 MHz < Frequency 80 MHz 80 MHz < Frequency 95 MHz 95 MHz < Frequency 108 MHz Wait State Requirement 2 3 4 5 6 7 8 9 Figure 10.7 8-Word Linear Synchronous Single Data Rate Burst with Wrap Around tCES 7 cycles for initial access is shown as an illustration. CE# 1 2 3 4 5 6 7 CLK tAVDS AVD# tACS tAVD Amax- A16 A/DQ15- A/DQ0 AC tACH AC DC tBACC tIACC DD DE DB OE# tRDY tOE tRACC Hi-Z tBDH RDY Notes 1. Figure shows for illustration the total number of wait states set to seven cycles. 2. The device is configured synchronous single data rate mode and RDY active with data. 3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the A/DQ15 - A/DQ0 pins to Hi-Z 68 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 10.8 8-Word Linear Single Data Read Synchronous Burst without Wrap Around tCES CE# 1 CLK tAVDS AVD# tACS Amax- A16 A/DQ15- A/DQ0 AC 7 cycles for initial access shown. 2 3 4 5 6 7 tAVD tACH AC tBACC tIACC DC DD DE DF D10 D13 tBDH OE# tCR RDY Hi-Z tRDYS tOE tRACC tRACC Notes 1. Figure shows for illustration the total number of wait states set to seven cycles. 2. The device is configured synchronous single data rate mode and RDY active with data. 3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the A/DQ15 - A/DQ0 pins to HI-Z 10.8.2 Asynchronous Mode Read Table 10.7 Asynchronous Mode Read Parameter Description JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ tCAS Access Time from CE# Low Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD# Address Hold Time from Rising Edge of AVD# Output Enable to Output Valid Read Output Enable Hold Time Toggle and Data# Polling Output Enable to High Z CE# Setup Time to AVD# Min Max Min 10 10 10 10 0 10 10 ns ns ns Typ Max Min Min Min Max Min 9 83 80 7.5 5 3.5 9 0 9 ns ns ns ns ns ns ns 66 MHz 83 MHz 108 MHz Unit February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 69 Data Sheet (Advance Information) Figure 10.9 Asynchronous Mode Read with Latched Addresses CE# tOE tOEH WE A/DQ15- A/DQ0 tCE RA tACC Amax- A16 AVD# tAVDP tAAVDS Note RA = Read Address, RD = Read Data. OE# tOEZ Valid RD RA tCAS tAAVDH =0ns Figure 10.10 Asynchronous Mode Read CE# tOE tOEH WE# A/DQ15- A/DQ0 tCE RA tACC Amax-A16 RA tAAVDH AVD# tAAVDS Note RA = Read Address, RD = Read Data. OE# tOEZ Valid RD tAVDP 10.8.3 Hardware Reset (RESET#) Table 10.8 Warm Reset Parameter Description JEDEC Std tRP tRH tRPH RESET# Pulse Width Reset High Time Before Read RESET# Low to CE# Low Min Min Min 50 200 10 ns ns s All Speed Options Unit 70 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 10.11 Reset Timings tRPH CE#, OE# tRH RESET# tRP 10.8.4 Erase/Program Timing Table 10.9 Erase/Program Timing Parameter Description JEDEC tAVAV tAVWL Standard tWC tAS Write Cycle Time (1) Synchronous Address Setup Time (2) Asynchronous Synchronous tWLAX tAH tAVDP tDVWH tWHDX tGHWL tDS tDH tGHWL tCAS tWHEH tWLWH tWHWL tCH tWP tWPH tSR/W tVID tVIDS tELWL tCS tAVSW tAVHW tSEA tESL tPSL tASP tPSP tERS tPRS Notes 1. Not 100% tested. 2. In asynchronous operation timing, addresses are latched on the rising edge of AVD#. 3. See the Erase and Programming Performance section for more information. Does not include the preprogramming time. Address Hold Time (2) Asynchronous AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to AVD# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations VPP Rise and Fall Time VPP Setup Time (During Accelerated Programming) CE# Setup Time to WE# AVD# Setup Time to WE# AVD# Hold Time to WE# Sector Erase Accept Time out Erase Suspend Latency Program Suspend Latency Toggle Time During Erase within a Protected Sector Toggle Time During Programming Within a Protected Sector Erase Resume to Erase Suspend Program Resume to Program Suspend Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Min Min Min 3.5 6 20 0 0 0 0 25 20 0 500 1 4 6 4 50 20 20 280 1 30 30 ns ns ns ns ns ns ns ns ns ns s ns ns ns s s s s s s s Min 4 3.5 ns Min 66 MHz 83 MHz 60 4 108 MHz Unit ns ns February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 71 Data Sheet (Advance Information) Figure 10.12 Asynchronous Program Operation Timings VIH Program Command Sequence (last two cycles) Read Status Data CLK VIL tAVSW tAVHW tAVDP AVD tAS Amax- A16 A/DQ15- A/DQ0 CE# 555h tAH PA VA In Progress VA 555h tCAS A0h PA PD tDS tD VA VA Complete OE# tW WE tCS tWPH tWC tVCS VCC tCH Notes 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. In progress and complete refer to status of program operation. 3. CLK can be either VIL or VIH. Figure 10.13 Chip/Sector Erase Command Sequence CLK VIH VIL Erase Command Sequence (last two cycles) tAVDP Read Status Data AVD tAS Amax- A16 A/DQ15- A/DQ0 2AAh tAH SA 555h for chip erase 10h for chip erase VA VA 2AAh 55h SA 30h tDS tDH VA In Progress VA Complete CE# OE# tWP WE tCS tVCS VCC Note SA is the sector address for Sector Erase. tCH tWPH tWC tWHWH2 72 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 10.14 Accelerated Unlock Bypass Programming Timing CE# AVD# WE# Amax- A16 A/DQ15- A/DQ0 OE# VPP VHH 1 s PA Don't Care A0h PA PD Don't Care tVIDS VIL or VIH Note Use setup and hold times from conventional program operation. Figure 10.15 Data# Polling Timings (During Embedded Algorithm) AVD# tCE CE# tCH OE tOEH WE# tACC Amax- A16 A/DQ15- A/DQ0 High Z tCEZ tOE tOEZ VA VA VA Status Data VA Status Data High Z Notes 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling outputs true data. Figure 10.16 Toggle Bit Timings (During Embedded Algorithm) AVD# CE# tCH OE tOEH WE# tACC Amax- A16 A/DQ15- A/DQ0 High Z tCE tOE tCEZ tOEZ VA VA VA Status Data VA High Z Status Data Notes 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits stop toggling. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 73 Data Sheet (Advance Information) Figure 10.17 Synchronous Data Polling Timings/Toggle Bit Timings CE# CLK AVD# Amax- A16 VA VA OE# A/DQ15- A/DQ0 tIACC tIACC VA Status Data VA Status Data RDY Notes 1. The timings are similar to synchronous read timings. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits stop toggling. 3. RDY is active with data (D8 = 0 in the Configuration Register). When D8 = 1 in the Configuration Register, RDY is active one clock cycle before data. Figure 10.18 DQ2 vs. DQ6 Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 10.19 Latency with Boundary Crossing Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. Address (hex) CLK AVD# (stays high) tRACC RDY (Note 1) RDY (Note 2) Data D124 D125 D126 latency 7C 7D 7E 7F 7F 80 81 82 83 tRACC tRACC latency tRACC D127 Invalid D128 D129 D130 OE#, (stays low) CE# Notes 1. RDY active with data (CR0.8 = 0 in the Configuration Register). 2. RDY active one clock cycle before data (CR0.8 = 1 in the Configuration Register). 3. Figure shows the device not crossing a bank in the process of performing an erase or program. 74 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Figure 10.20 Wait State Configuration Register Setup Data D0 D1 AVD# total number of clock cycles following addresses being latched OE# 1 CLK 2 3 4 5 6 7 Rising edge of next clock cycle following last wait state triggers next burst data 0 1 2 3 4 5 6 7 Total number of clock edges following addresses being latched Table 10.10 Example of Programmable Wait States CR1.0 CR0.13 CR0.12 Programmable Wait State (See Note) 0000 0001 0010 0011 0100 0101 0110 = 0111 1000 CR0.11 = 1001 ... initial data is valid on the 8th 9th rising CLK edge after addresses are latched Reserved = initial data is valid on the 2nd 3rd 4th 5th 6th 7th rising CLK edge after addresses are latched 1101 ... = initial data is valid on the 13th rising CLK edge AVD# transition to VIH (Default) 1110 1111 Note The addresses are latched by rising edge of CLK. = Reserved February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 75 Data Sheet (Advance Information) Figure 10.21 Back-to-Back Read/Write Cycle Timings Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) In same bank and/or array data from other bank Begin another write or program command sequence tWC CE# tRC tRC tWC OE# tOE tOEH WE# tWP tWP tDS A/DQ15- A/DQ0 PA/SA PD/30h tGHWL tACC tDH RA RD tOEZ tOEH RA RD 555h AAh tSR/W Amax- A16 PA/SA RA RA 555h tAS AVD# tAH Note Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy bank. The system should read status twice to ensure valid information. 76 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 10.9 Erase and Programming Performance Table 10.11 Erase and Programming Performance Parameter 64 Kword 16 Kword Sector Erase Time 64 Kword 16 Kword 64 Kword 16 Kword Sector Erase Time 64 Kword 16 Kword VCC VCC VPP VPP VCC VCC VPP VPP VCC VCC VPP Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time VCC VPP VCC VPP VCC Chip Programming Time (using 32 word buffer) VPP Erase Suspend/Erase Resume Program Suspend/Program Resume Min Min Typ (1) 0.8 0.15 0.8 0.15 0.90 0.45 0.70 0.35 77 (NS128P) Chip Erase Time 154 (NS256P) 306 (NS512P) 40 24 9.4 6 300 192 78.6 (NS128P) 157.3 (NS256P) 314.6 (NS512P) 51 (NS128P) 101 (NS256P) 202 (NS512P) Word Programming Time Max (2) 3.5 2.0 3.5 2.0 s 5.00 1.85 3.75 1.40 154 (NS128P) 308 (NS256P) 612 (NS512P) 400 s 240 94 60 s 3000 1920 157.3 (NS128P) 314.6 (NS256P) 629.2 (NS512P) s 102 (NS128P) 202 (NS256P) 404 (NS512P) 20 20 s s Excludes system level overhead (4) Excludes system level overhead (4) s Includes 00h programming prior to erasure (3) Excludes 00h programming prior to erasure (3) Unit Comments Notes 1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles using checkerboard patterns. 2. Under worst case conditions of 90C, VCC = 1.70 V, 100,000 cycles. 3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11.1, Memory Array Commands on page 78 and Table 11.2, Sector Protection Commands on page 80for further information on command definitions. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 77 Data Sheet (Advance Information) 11. Appendix This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see www.spansion.com. Table 11.1 Memory Array Commands Bus Cycles (1, 2, 3, 4, 5, 6) Command Sequence (Notes) Cycles First Addr RA XXX 555 Data (19) RD F0 AA 2AA 55 (BA) 555 (BA) 555 (BA) 555 (SA) 555 (BA) 555 555 SA 90 (BA) X00 (BA) X01 (BA) X07 (SA) X02 (BA) X03 PA SA Data WC PA PD WBL PD 0001 (BA)X 0E (BA) X0F Second Addr Data (19) Third Addr Data (19) Fourth Addr Data (19) Fifth Addr Data (19) Sixth Addr Data (19) Asynchronous Read (7) Reset (8) Manufacturer ID 1 1 4 Device ID (10) 6 555 AA 2AA 55 90 3x7E (10) (10) Autoselect (9) Indicator Bits Sector Unlock/Lock Verify (11) Revision ID 4 555 AA 2AA 55 90 (12) 0000/ 0001 4 555 AA 2AA 55 90 4 4 6 1 3 6 6 1 1 5 4 555 555 555 SA 555 555 555 BA BA 555 555 (BA) 55 555 XX XX XX XX XX AA AA AA 29 AA AA AA B0 30 AA AA 2AA 2AA 2AA 55 55 55 90 A0 25 Single Word Program Write to Buffer (17) Write Buffer to Flash Write to Buffer Abort Reset (10) Chip Erase Sector Erase Program/Erase Suspend (15) Program/Erase Resume (16) Set Configuration Register (21, 22, 24) Read Configuration Register 2AA 2AA 2AA 55 55 55 555 555 555 F0 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 2AA 2AA 55 55 555 555 D0 C6 X00 X0 (0 or 1) CR0 CR (0 or 1) X01 CR1 CFI Query (17) Unlock Bypass Entry (18) Unlock Bypass Program (13), (14) Unlock Bypass Mode (23) Unlock Bypass Sector Erase (13), (14) Unlock Bypass Erase (13), (14) Unlock Bypass CFI (13), (14) Unlock Bypass Reset Legend X = Don't care. RA = Read Address. RD = Read Data. 1 3 2 2 2 1 2 98 AA A0 80 80 98 90 XXX 00 2AA PA SA XXX 55 PD 30 10 555 20 PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address. NS128P = A22 - A14; NS256P = A23 - A14. 78 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) BA = Bank Address. NS128P = A22 - A20, and A19; NS064P = A21, A20 - A18; NS256P = A23 - A20.CR = Configuration Register data bits D15 - D0. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes 1. See Table 6.1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15 - DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3 - PWD0. 5. Unless otherwise noted, address bits Amax - A14 are don't cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect address is a read cycle. The system must provide the bank address. 10. (BA) + 0Eh ----> For NS128 = 43h, NS256 = 41h, NS512 = 3Fh (BA) + 0Fh ----> For NS128/256/512 = 00h 11. The data is 0000h for an unlocked sector and 0001h for a locked sector 12. See Table 6.12, Autoselect Addresses on page 34. 13. The Unlock Bypass command sequence is required prior to this command sequence. 14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Program/Erase Suspend command is valid only during a program/ erase operation, and requires the bank address. 16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address. 17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 18. Write Buffer Programming can be initiated after Unlock Bypass Entry. 19. Data is always output at the rising edge of clock. 20. Do not enter wrong address or data cycles. 21. Do not use 0x30 for CR data (otherwise in the erase suspend --> CR read or set sequence, the device will go into erase resume instead of CR read or set). 22. Software reset is needed after CR read (otherwise the device is still in CR read mode). 23. When device is in Unlock Bypass mode, do not enter another command before Unlock Bypass reset command is issued). 24. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers retain their previous settings. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 79 Data Sheet (Advance Information) Table 11.2 Sector Protection Commands Bus Cycles 1, 2, 3, 4, 5, 6 Command Sequence (Notes) Cycles First Addr 555 555 00 555 555 XX 00 XX 555 XX Data (10) AA AA data AA AA A0 data 90 AA A0 PWD 0 25 90 AA A0 80 RD(0) 90 XX 00 XX 2AA 00/ 01/ 02/03 01 00 XX 2AA (BA) SA SA0 00 55 PWD0/ 1/ 2/3/ PWD1 03 00 55 00 30 (BA) 555 C0 02 00 PWD 2 PWD 0 03 01 PWD 3 PWD 1 02 PWD 2 03 PWD 3 00 29 555 60 2AA 2AA 00 55 55 data 555 555 90 40 XX 00 Second Addr 2AA 2AA Data (10) 55 55 Third Addr 555 555 Data (10) 88 A0 PA PD Fourth Addr Data (10) Fifth Addr Data (10) Sixth Addr Data (10) Seventh Addr Data (10) Entry (5) Secured Silicon Program Read Exit (7) Register Command Set Entry (5) Register Bits Program (6) Register Bits Read Register Command Set Exit (7) Protection Command Set Entry Program (9) Password 3 4 1 4 3 2 1 2 3 2 Register Lock Read Password (10) Unlock (9) Protection Command Set Exit Non-Volatile Sector Protection Command Set Entry (5) Program 4 7 2 3 2 2 1 2 00 00 XX 555 XX XX (BA) SA XX PPB All Erase (8) Status Read Non-Volatile Sector Protection Command Set Exit (7) Global Volatile Sector Protection Freeze Command Set Entry (5) Set Status Read Global Volatile Sector Protection Freeze Command Set Exit (7) Volatile Sector Protection Command Set Entry (5) Set 3 2 1 2 555 XX XX XX AA A0 RD(0) 90 2AA XX 55 00 555 50 PPB Lock Bit XX 00 (BA) 555 3 2 2 1 2 2 2 1 4 1 555 XX XX (BA) SA XX 555 555 RA SA SA AA A0 A0 RD(0) 90 A0 80 RD 25 29 2AA (BA) SA (BA) SA 55 00 01 E0 DYB Clear Status Read Volatile Sector Protection Command Set Exit (7) Program XX PA SA 00 Data 30 Accelerated Sector Erase Asynchronous Read Write to Buffer Program Buffer to Flash SA WC PA PD WBL PD Legend X = Don't care 80 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) RA = Read Address. RD = Read Data. PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address. NS128P = A22 - A14, NS256P = A23 - A14. BA = Bank Address. NS128P = A22 - A20, and A19; NS256P = A23 - A20. CR = Configuration Register data bits D15 - D0. PWD3 - PWD0 = Password Data. PD3 - PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes 1. See Table 6.1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15 - DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3 - PWD0. 5. Unless otherwise noted, address bits Amax - A14 are don't cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The data is 0000h for an unlocked sector and 0001h for a locked sector. 9. The Exit command must be issued to reset the device into read mode, otherwise the device hangs. 10. Data is always output at the rising edge of clock. 11.1 Common Flash Memory Interface The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward-compatible and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 11.3 - 11.6) within that bank. All reads outside of the CFI address range, within the bank, returns non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: CFI Entry command */ *( (UINT16 *)bank_addr + 0x0055 = 0x0098; /* Example: CFI Exit command */ *( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write CFI entry command */ /* write cfi exit command */ For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents. February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 81 Data Sheet (Advance Information) Table 11.3 CFI Query Identification String Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string QRY Description Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 11.4 System Interface String Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0017h 0019h 0000h 0000h 0005h 0009h 000Ah 0000h 0003h 0002h 0002h 0000h VCC Min. (write/erase) D7 - D4: volt, D3 - D0: 100 millivolt VCC Max. (write/erase) D7 - D4: volt, D3 - D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical Program Time per single word write 2N s (for example, 30 s) Typical Program Time using buffer 2N s (for example, 300us) (00h = not supported) Typical time for sector erase 2N ms Typical time for full chip erase 2N ms (00h = not supported) Max. Program Time per single word [2N times typical value] Max. Program Time using buffer [2N times typical value] Max. time for sector erase [2N times typical value] Max. time for full chip erase [2N times typical value] (00h = not supported) Description Table 11.5 Device Geometry Definition (Sheet 1 of 2) Addresses 27h 28h 29h 2Ah 2Bh 2Ch Data 0018h (NS128P) 0019h (NS256P) 001Ah (NS512P) 0001h 0000h 0006h 0000h 0002h (NS128P) 0002h (NS256P) 0001h (NS512P) 007Eh (NS128P) 00FEh (NS256P) 01FFh (NS512P) 0000h 0000h 0002h 0003h (NS128P) 0003h (NS256P) 0000h (NS512P) 0000h 0080h (NS128P) 0080h (NS256P) 0000h (NS512P) 0000h [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 2 Information (Small Sector Section) [lower byte] - Number of sectors. Device Size = 2N byte Flash Device Interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte] [upper byte] (00h = not supported) Max. number of bytes in multi-byte buffer write = 2N [lower byte] [upper byte] (00h = not supported) Number of Erase Block Regions within device 01h = Uniform Sector; 02h = Boot + Uniform; 03h = Boot + Uniform + Boot Description 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Erase Block Region 1 Information (Large Sector Section) [lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors... 03h=4 sectors [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] 82 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) Table 11.5 Device Geometry Definition (Sheet 2 of 2) Addresses 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Description Erase Block Region 3 Information [lower byte] - Number of sectors. 00h=1 sector; 01h=2 sectors... 03h=4 sectors [upper byte] [lower byte] - Equation =>(n = Density in Bytes of any 1 sector/256)h [upper byte] Erase Block Region 4 Information Table 11.6 Primary Vendor-Specific Extended Query (Sheet 1 of 2) Addresses 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0034h Query-unique ASCII string PRI Major CFI version number, ASCII Minor CFI version number, ASCII Address Sensitive Unlock (Bits 1 - 0) 00b = Required, 01b = Not Required Silicon Technology (Bits 5 - 2) 0011b = 130 nm; 0100b = 110 nm; 0101b = 90 nm 001010b = 000Ah Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protection per Group 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08h = Advanced Sector Protection; 07h = New Sector Protection Scheme Simultaneous Operation Number of Sectors in all banks except bank0 Burst Mode Type 00 = Not Supported, 01 = Supported Not supported VPP (Acceleration) Supply Minimum 00h = Not Supported, D7 - D4: Volt, D3 - D0: 100 mV VPP (Acceleration) Supply Maximum 00h = Not Supported, D7 - D4: Volt, D3 - D0: 100 mV Write Protect Function 00h = No Boot, 01h = Dual Boot, 02h = Bottom Boot, 03h = Top Boot, 04h = Uniform Bottom, 05h = Uniform Top, 06h = All Sectors Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01=Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns (for example, 10 s => n=14) Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns (for example, 10 s => n=14) Erase Suspend Time-out Maximum 2N s Program Suspend Time-out Maximum 2N s Bank Organization: X = Number of banks Bank 0 Region Information. X = Number of sectors in bank Description 45h 0014h 46h 47h 48h 49h 0002h 0001h 0000h 0008h 0078h (NS128P) 00F0h (NS256P) 01E0h (NS512P) 0001h 0000h 0085h 0095h 0003h (NS128P) 0003h (NS256P) 0005h (NS512P) 0001h 0001h 0008h 0014h 0014h 0005h 0005h 0010h 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 83 Data Sheet (Advance Information) Table 11.6 Primary Vendor-Specific Extended Query (Sheet 2 of 2) Addresses 59h Data 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 0008h (NS128P) 0010h (NS256P) 0020h (NS512P) 000Bh (NS128P) 0013h (NS256P) 0020h (NS512P) Description Bank 1 Region Information. X = Number of sectors in bank 5Ah Bank 2 Region Information. X = Number of sectors in bank 5Bh Bank 3 Region Information. X = Number of sectors in bank 5Ch Bank 4 Region Information. X = Number of sectors in bank 5Dh Bank 5 Region Information. X = Number of sectors in bank 5Eh Bank 6 Region Information. X = Number of sectors in bank 5Fh Bank 7 Region Information. X = Number of sectors in bank 60h Bank 8 Region Information. X = Number of sectors in bank 61h Bank 9 Region Information. X = Number of sectors in bank 62h Bank 10 Region Information. X = Number of sectors in bank 63h Bank 11 Region Information. X = Number of sectors in bank 64h Bank 12 Region Information. X = Number of sectors in bank 65h Bank 13 Region Information. X = Number of sectors in bank 66h Bank 14 Region Information. X = Number of sectors in bank 67h Bank 15 Region Information. X = Number of sectors in bank 84 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 Data Sheet (Advance Information) 12. Revision History Section Revision A (June 29, 2006) Initial release Revision A1 (February 20, 2007) The tAVDS specification is changed from 4 ns to 5 ns The wait state for 83 MHz is changed to 8 ICC3(Max) is changed to 70 A and ICC6(Max) is changed to 40 A VIL (Min) is changed to -0.2 V tOE (Max) in both Asynchronous & Synchronous modes is changed to 9 ns across all frequencies tCEZ (Max) is changed to 10 ns across all frequencies Global tOEZ (Max) in both Asynchronous & Synchronous modes is changed to 10 ns across all frequencies tACH(Min) is changed to 6 ns (66 MHz) and 5 ns (83 MHz and 108 MHz) tRDY(Max) is changed to 10 ns tRACC(Max) is changed to 7.6 ns for 108 MHz tOEH(Min) in Asynchronous mode is changed to 10 ns for 108 MHz Erase and Programing Performance table is updated tCE in Asynchronous mode is changed to 83ns Description February 20, 2007 S29NS-P_00_A1 S29NS-P MirrorBitTM Flash Family 85 Data Sheet (Advance Information) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2005-2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 86 S29NS-P MirrorBitTM Flash Family S29NS-P_00_A1 February 20, 2007 |
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